Memory with I/O mappable redundant columns

Details Memory with I/O mappable redundant columns Memory with I/O mappable redundant columns

1993-05-06

1994-02-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, 365200, 36518902, 36523003, 371 103, G11C 700

Patent

active

052873102

ABSTRACT:
A byte-wide memory has a plurality of redundant columns. Each redundant column is capable of being mapped to any one of a plurality of input buffers and output buffers in place of a defective column. Fuse match logic circuits store the addresses of defective columns. I/O fuse decoder circuits are coupled to the fuse match logic circuits and store information identifying the input and output buffers associated with each defective column. The redundant columns are selected in response to a portion of the column address signals which select nonredundant columns. When a received column address matches a stored column address, the redundant column selected by the portion of column address signals is mapped to the input and output buffer associated with the defective column in place of the defective column.

REFERENCES:
patent: 4601019 (1986-07-01), Shah et al.
patent: 4604730 (1986-08-01), Yoshida et al.
patent: 4807056 (1989-03-01), Furutani et al.
patent: 4849938 (1989-07-01), Furutani et al.
patent: 5043943 (1991-08-01), Crisp et al.

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