Memory with improved write mode to read mode transition

Details Memory with improved write mode to read mode transition Memory with improved write mode to read mode transition

1986-03-03

1987-08-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1140

Patent

active

046897712

ABSTRACT:
A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.

REFERENCES:
patent: 4644500 (1987-02-01), Yonezu et al.
patent: 4651308 (1987-03-01), Sato

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