Memory with improved reading time

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365185, 365208, G11C 1604

Patent

active

051777070

ABSTRACT:
To shorten the reading cycle of a memory, the memory cells of which comprise floating gate transistors, a circuit for pre-charging the bit lines of the memory is used, this circuit being independent of the reading sense amplifier proper. This pre-charging circuit includes a differential amplifier receiving, firstly, a voltage signal for the effective pre-charging of the bit line and, secondly, a pre-charging voltage reference signal. So long as the effective pre-charging has not reached the assigned value, the differential amplifier delivers a command signal to a power transistor that pre-charges the bit lines. As soon as the assigned pre-charging value is reached, the power transistor goes off, and the circuit of the amplifier is itself uncoupled.

REFERENCES:
patent: 4713797 (1987-12-01), Morton et al.
patent: 4879682 (1989-11-01), Engles
patent: 4908795 (1990-03-01), Tsuchiya et al.
Patent Abstracts of Japan, vol. 5, No. 185 (P-091) Nov. 25, 1981 and JP-A-56 114 193.

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