Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-01-18
2001-10-30
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S203000, C365S230030
Reexamination Certificate
active
06310811
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices such as ROM (Read Only Memory) and EPSOM(Erasable and Programmable Read Only Memory) can store data in a memory cell transistor in a binary or multi-value form. In these semiconductor memory devices, a plurality of memory cell transistors are arranged in a matrix. That is, the plurality of memory cells are connected with word lines in a row direction and is connected with digit lines in a column direction. When a storage data is to be read out from a memory cell, bias voltages are applied to the word line and the digit line which are determined in accordance with an address signal. In this way, a quantity of current flowing through the memory cell is sensed and the storage data is read out.
In a conventional semiconductor memory device, each of memory cell transistors is segmented by an element separation area. The source of the memory cell transistor is grounded, the gate thereof is connected with a word line and the drain thereof is connected with a digit line. In such a structure, the structure of the reading circuit can be simplified. However, because a contact with the drain of the memory cell transistor must be formed for every memory cell, the structure is unsuitable for the reduction of a chip area.
To solve such a problem, the arrangement of memory cells of a virtual ground system is proposed. In the semiconductor memory device of this system in which the plurality of memory cell transistors are arranged in a matrix, the source of drain of a memory cell transistor are connected with digit lines in common. Moreover, the source or drain of the memory cell transistor is connected with the source or drain of a neighbor memory cell transistor. For these reasons, the number of drain contacts or source contacts can be reduced and the chip area can be greatly reduced.
When a storage data is read out from a memory cell in the virtual ground system, bias voltages are applied to a selected word line and a selected digit line which are determined in accordance with an address signal, as in the case mentioned above. A quantity of current flowing through the memory cell at this time is sensed by a sense amplifier and the storage data is read. However, the selected digit line to which the memory cell is connected is also connected with a neighbor memory cell which is connected with the same selected word line as the memory cell. Therefore, the bias voltage which has been supplied to a selected digit line diffusion wiring line is supplied to not only the memory cell as the reading operation object but also the neighbor memory cell. Therefore, a read current also flows through the neighbor memory cell through a non-selected digit line diffusion wiring line. As the result, the semiconductor memory device outputs a wrong data. In this way, it is necessary that the non-selected digit line diffusion wiring line is precharged to a level equal to the selected digit line diffusion wiring line. In this case, the read current flows only through the selected memory cell which is connected with the selected digit line diffusion wiring line.
FIG. 1
shows a block diagram of a conventional example of a semiconductor memory device. Referring to
FIG. 1
, the structure and operation of the semiconductor memory device will be described.
The conventional example of the semiconductor memory device such as a ROM and an EPSOM is composed of an address buffer
51
, a Y decoder
52
, a Y selector
53
, a bank decoder
54
, an X decoder
55
, a virtual ground (GND) selector
56
, a memory cell array in a memory cell matrix
59
, a precharging circuit
60
, a reference memory cell section
61
, a sensing circuit
62
, a latch circuit
63
, an output buffer
64
, a control signal buffer circuit
65
, an address transition detecting circuit
66
, and a discharge control circuit
67
. The memory cell matrix
59
is composed of a memory cell array
58
and a bank selector
57
.
The address buffer
51
once holds an address signal AD supplied from an external unit such as a microprocessor, and outputs to the X decoder
55
, the Y decoder
52
, the bank decoder
54
, the virtual ground selector
56
, and the address transition detecting circuit
66
. The X decoder
55
decodes the address signal AD and selects one of word line selection signals W
00
to W
63
to set a row of memory cells in the memory cell array
58
to a read and write enable state. The Y decoder
52
decodes the address signal AD and supplies a Y decoding signal to the Y selector
53
. The Y selector
53
selects one of digit lines D
0
to D
4
in response to the Y decoding signal, to set one column of memory cells in the memory cell array
58
to a read enable state. Also, the Y selector
53
supplies predetermined bias voltages to ones of the digit lines D
0
to D
4
which are selected by the sensing circuit
62
and the precharging circuit
60
.
The bank decoder
54
decodes the address signal AD and supplies one of bank selection signals BS
1
to BS
6
to the bank selector
57
. The bank selector
57
connects or disconnects a predetermined digit line diffusion wiring line (not shown) in memory cell array
58
to or from the sensing circuit
62
, the precharging circuit
60
and the virtual ground selector
56
in accordance with the bank selection signal BS
1
to BS
6
. It should be noted that the bank selector
57
is collectively shown on the memory cell matrix
59
in FIG.
1
. However, the bank selector
57
is divided into a first bank selector and a second bank selector, as mentioned later. The first bank selector selects the connection of the memory cell array
58
to the sensing circuit
62
and the precharging circuit
60
, and the second bank selector selects the connection of the memory cell array
58
to the sensing circuit
62
and the virtual ground selector
56
. The virtual ground selector
56
selects one of virtual ground lines VG
1
to VG
3
connected with the memory cell matrix
59
in accordance with the address signal AD from the address buffer
51
to supplies a ground potential GND or a power supply potential Vcc.
The memory cell matrix
59
is composed of the memory cell array
58
and the bank selector
57
. The memory cell array
58
is composed of the plurality of memory cells which are arranged in a matrix, and a storage data is read out from the selected memory cell in accordance with the address signal AD. The precharging circuit
60
supplies the bias voltage to a non-selected memory cell in accordance with the position of the selected memory cell in the memory cell matrix
59
. As a result, it can be prevented that the current flowing through the selected memory cell flows through the non-selected memory cell. Thus, the storage data can be surely read out. A precharge signal PC is supplied from the precharging circuit
60
to the selected digit line through a switching operation by the Y selector
53
in accordance with the address signal AD.
The reference memory cell section
61
generates a reference digit line signal DGR which is used to distinguish a read digit line signal when the storage data is read out from the selected memory cell of the memory cell matrix
59
. The sensing circuit
62
compares the reference digit line signal DGR which is outputted from the reference memory cell section
61
and a digit line signal DG which is outputted from the memory cell matrix
59
. Thus, the sensing circuit
62
senses the storage data which has been stored in the selected memory cell of the memory cell matrix
59
and outputs a sense output signal SO to the latch circuit
63
. The control signal buffer circuit
65
generates various control signals used in the semiconductor memory device in accordance with a chip select signal CE, a read instruction signal RD, and an output enable signal OE which are supplied from the external unit such as the microprocessor. In
FIG. 1
, only the chip select signal CE is shown.
The address transi
McGinn & Gibb PLLC
NEC Corporation
Zarabian A.
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