Memory structure for providing decreased leakage and bipolar...
Memory system for storing data from variable numbers of input da
Memory with a combined global data line load and multiplexer
Memory, processing system and methods for use therewith
Merged Memory and Logic (MML) integrated circuits including data
Merged memory and logic (MML) integrated circuits including inde
Method and apparatus for 1 of 4 register file design
Method and apparatus for a multiplexed address line driver
Method and apparatus for address and data line usage in a...
Method and apparatus for alternate operation of a random...
Method and apparatus for global bitline multiplexing for a...
Method and apparatus for in-system redundant array repair on...
Method and apparatus for in-system redundant array repair on...
Method and apparatus for multi-bit register cell
Method and apparatus for multiple context and high...
Method and apparatus for reducing failures due to bit line coupl
Method of multiplexed data reading/writing suitable for video-on
Methods and apparatus for reading memory device register data
Multi-stage output multiplexing circuits and methods for...
Multiple word width memory array clocking scheme