Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2005-07-05
2005-07-05
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S230020
Reexamination Certificate
active
06914829
ABSTRACT:
An output multiplexing circuit for a Double Data Rate (DDR) synchronous memory device includes n first latches, n first switches, n second switches, n second latches, and two third switches. The n first latches simultaneously prefetch n-bit data transmitted from a memory cell array via a data path. The n first switches simultaneously transfer the n-bit data prefetched into the first latches to n nodes in response to a CAS latency information signal. The n second switches simultaneously transfer data on the nodes in response to n signals that are synchronized with a clock signal and sequentially generated at a predetermined interval. The n second latches store the data transferred via the second switches. The two third switches sequentially transfer the data stored in the n second latches to an input terminal of an output driver of the memory device at a rising edge and a falling edge of a delay signal of the clock signal. Analogous methods also are described.
REFERENCES:
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6134180 (2000-10-01), Kim et al.
patent: 6337830 (2002-01-01), Faue
patent: 6600691 (2003-07-01), Morzano et al.
patent: 6741521 (2004-05-01), Kono
Myers Bigel & Sibley & Sajovec
Phan Trong
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