Merged Memory and Logic (MML) integrated circuits including data

Details Merged Memory and Logic (MML) integrated circuits including data Merged Memory and Logic (MML) integrated circuits including data

1997-12-31

1999-07-20

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

365201, G11C 700

Patent

active

059264209

ABSTRACT:
Merged Memory and Logic (MML) integrated circuits include data path width reducing circuits and methods that are responsive to a test mode signal. In particular, MML circuits include a memory block, a logic block and a first plurality of output data paths that interconnect the memory block and the logic block. A data path width reducing circuit is responsive to a test mode signal, to serially provide output data on the first plurality of output data paths to at least one MML integrated circuit output pad, wherein the number of MML integrated circuit output pads is less than the first plurality. The external data path of the MML integrated circuit is thereby reduced during the test mode. The MML integrated circuit may also include a second plurality of input data paths that interconnect the memory block and the logic block. The data path width reducing circuit also serially provides input data from at least one MML integrated circuit input pad to the second plurality of input data paths wherein the number of MML integrated circuit input pads is less than the second plurality. Preferably, the first and second pluralities are identical and the number of MML integrated circuit input pads and output pads are identical.

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Search Report, GB 9802819.4, Jul. 8, 1998.

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