Method and apparatus for reducing failures due to bit line coupl

Details Method and apparatus for reducing failures due to bit line coupl Method and apparatus for reducing failures due to bit line coupl

1996-11-08

1998-11-10

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Multiplexing

365203, 365227, G11C 700

Patent

active

058354212

ABSTRACT:
A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a second voltage level. After data has been read from the memory (10), the first group of bit lines (22) is discharged to the second voltage level.

REFERENCES:
patent: 4417326 (1983-11-01), Toyoda et al.
patent: 4667311 (1987-05-01), Ul Haq et al.
patent: 5062079 (1991-10-01), Tsuchida et al.
patent: 5099452 (1992-03-01), Yamakoshi et al.
patent: 5398207 (1995-03-01), Tsuchida et al.
patent: 5453955 (1995-09-01), Sakui et al.
patent: 5526319 (1996-06-01), Dennard et al.

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