Multiple word width memory array clocking scheme

Details Multiple word width memory array clocking scheme Multiple word width memory array clocking scheme

1995-11-17

1998-01-27

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

365219, 365221, 365236, G11C 700

Patent

active

057128200

ABSTRACT:
The present invention provides a circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

REFERENCES:
patent: 4467443 (1984-08-01), Shima
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 4839866 (1989-06-01), Ward et al.
patent: 4864543 (1989-09-01), Ward et al.
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 4985867 (1991-01-01), Ishii et al.
patent: 5084837 (1992-01-01), Matsumoto et al.
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5220529 (1993-06-01), Kohiyama
patent: 5222047 (1993-06-01), Matsuda et al.
patent: 5228002 (1993-07-01), Huang
patent: 5262996 (1993-11-01), Shiue
patent: 5265063 (1993-11-01), Kogure
patent: 5305253 (1994-04-01), Ward
patent: 5311475 (1994-05-01), Huang
patent: 5317756 (1994-05-01), Komatsu et al.
patent: 5345419 (1994-09-01), Fenstermaker et al.
patent: 5367486 (1994-11-01), Mori et al.
patent: 5375092 (1994-12-01), Taniguchi et al.
patent: 5404332 (1995-04-01), Sato et al.
patent: 5406273 (1995-04-01), Nishida et al.
patent: 5406554 (1995-04-01), Parry
patent: 5412611 (1995-05-01), Hattori
patent: 5426612 (1995-06-01), Ichige et al.
patent: 5467319 (1995-11-01), Nusinov et al.
patent: 5490257 (1996-02-01), Hoberman et al.
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5506815 (1996-04-01), Hsieh
patent: 5513318 (1996-04-01), van de Goor et al.
patent: 5521876 (1996-05-01), Hattori et al.
patent: 5528553 (1996-06-01), Saxena
patent: 5546347 (1996-08-01), Ko et al.

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