Memory structure for providing decreased leakage and bipolar...

Details Memory structure for providing decreased leakage and bipolar... Memory structure for providing decreased leakage and bipolar...

2007-04-24

2007-04-24

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S203000, C365S189110

Reexamination Certificate

active

11221637

ABSTRACT:
A memory circuit. In one embodiment, the memory circuit includes a first one-hot multiplexer having a first plurality of local bitlines and a second one-hot multiplexer having a second plurality of local bitlines. Each of the first and second pluralities of local bitlines includes is coupled to a memory cell, and includes a passgate arranged on its respective local bitline to allow access to the cell. The first one-hot multiplexer and the second one-hot multiplexer are coupled together such that the highest order local bitline (i.e. corresponding the highest order bit in the group) is coupled to the lowest order bitline of the second one-hot multiplexer, and vice-versa.

REFERENCES:
patent: 5615144 (1997-03-01), Kimura et al.
patent: 6683805 (2004-01-01), Joshi et al.
patent: 6952377 (2005-10-01), Chung
patent: 6957372 (2005-10-01), Barth, Jr. et al.
patent: 6958931 (2005-10-01), Yoon

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