Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2000-09-14
2001-09-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S063000
Reexamination Certificate
active
06292401
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to a global bitline multiplexing approach that may be used for high-speed memory.
2. Discussion of Related Art
High-speed memory design has become increasingly important to the overall performance of processors and systems, for example. One of the larger components of memory latency and, therefore, keys to high performance memory design, may be bitline sensing. For a cache memory, for example, bitline sensing can account for as much as two thirds of total cache latency.
A conventional memory
100
may be arranged as shown in FIG.
1
. For the configuration shown in
FIG. 1
, one global bitline
105
is provided for each column
101
and
102
of memory cells. While only two columns of memory cells are shown in
FIG. 1
, it will be appreciated that the memory
100
may include a larger number of columns of memory cells with an additional global bitline being provided for each additional column of memory. Further, where the memory is a multi-ported memory, there may be multiple global bitlines per column of memory to correspond to the multiple ports (i.e. one global bitline per column per port).
Local bitlines
107
are coupled to clusters of memory cells such as the clusters
111
-
114
of memory cells. The clusters of memory cells
111
-
114
may include, for example, eight memory cells. The memory
100
may include additional clusters of memory cells in each column.
In operation, in response to a read request, local bitline(s)
107
coupled to a memory row to be read indicate a logical value stored in a corresponding memory cell. If any local bitline
107
coupled to a global bitline indicates a logical zero value, the corresponding global bitline (through a NAND gate
115
in this example) is pulled down. Thus, for the example of
FIG. 1
, multiple global bitlines are typically switched in response to a memory read request if more than one memory cell in the row being read stores a logical zero value.
In response to a column select signal, a multiplexer (mux)
120
then selects between signals communicated over multiple global bitlines
105
and outputs the selected data. Multiple levels of multiplexing (not shown) may be used to provide the desired output data in response to the read request.
In the memory
100
, because global bitlines may be switched even when a corresponding column is not selected to be read, power consumption of such a memory may be unnecessarily and undesirably high.
REFERENCES:
patent: 5561626 (1996-10-01), Fujii
patent: 5701269 (1997-12-01), Fujii
patent: 5828594 (1998-10-01), Fujii
patent: 6091633 (2000-07-01), Cernea et al.
Fletcher Thomas D.
Zhang Kevin X.
Faatz Cynthia T.
Intel Corporation
Nguyen Tan T.
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