Method and apparatus for a multiplexed address line driver

Details Method and apparatus for a multiplexed address line driver Method and apparatus for a multiplexed address line driver

2007-03-27

2007-03-27

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S185240, C365S189090

Reexamination Certificate

active

10971394

ABSTRACT:
A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory cell address line during Power On Reset (POR) to insure proper memory cell initialization during power up. Once initialized, read and write address select signals are level shifted to be equal to or greater than the read and write voltage magnitudes applied to the memory cell address line to ensure proper operation.

REFERENCES:
patent: 5317212 (1994-05-01), Wahlstrom
patent: 6335896 (2002-01-01), Wahlstrom
patent: 6567309 (2003-05-01), Tanzawa
patent: 6859411 (2005-02-01), Pfeiffer et al.
patent: 7009881 (2006-03-01), Noguchi
U.S. Appl. No. 10/796,750, filed Mar. 8, 2004, Vadi et al.
U.S. Appl. No. 10/970,964, filed Oct. 22, 2004, Vadi et al.

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