256 Meg dynamic random access memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S230080

Reexamination Certificate

active

07489564

ABSTRACT:
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

REFERENCES:
patent: 4905191 (1990-02-01), Arai
patent: 4970725 (1990-11-01), McEnroe et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 5159273 (1992-10-01), Wright et al.
patent: 5212440 (1993-05-01), Waller
patent: 5231605 (1993-07-01), Lee
patent: 5266821 (1993-11-01), Chern et al.
patent: 5359557 (1994-10-01), Aipperspach et al.
patent: 5373227 (1994-12-01), Keeth
patent: 5379263 (1995-01-01), Ogawa et al.
patent: 5384784 (1995-01-01), Mori et al.
patent: 5457696 (1995-10-01), Mori
patent: 5481179 (1996-01-01), Keeth
patent: 5517454 (1996-05-01), Sato et al.
patent: 5519360 (1996-05-01), Keeth
patent: 5526364 (1996-06-01), Roohparvar
patent: 5552739 (1996-09-01), Keeth et al.
patent: 5555249 (1996-09-01), Hilley et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5568428 (1996-10-01), Toda
patent: 5574697 (1996-11-01), Manning
patent: 5608674 (1997-03-01), Yabe et al.
patent: 5614859 (1997-03-01), Ong
patent: 5651011 (1997-07-01), Keeth
patent: 5661729 (1997-08-01), Miyazaki et al.
patent: 5677645 (1997-10-01), Merritt
patent: 5706234 (1998-01-01), Pilch et al.
patent: 5724289 (1998-03-01), Watanabe
patent: 5838150 (1998-11-01), Keeth
patent: 5901105 (1999-05-01), Ong et al.
patent: 5960455 (1999-09-01), Bauman
patent: 5983375 (1999-11-01), Kim et al.
patent: 5999480 (1999-12-01), Ong et al.
patent: 6043118 (2000-03-01), Suwanai et al.
patent: 6198687 (2001-03-01), Sakui et al.
patent: 6324088 (2001-11-01), Keeth et al.
patent: 6473346 (2002-10-01), Kim et al.
patent: 2002/0008984 (2002-01-01), Keeth et al.
Yoo et al., “A 32-Bank 1Gb DRAM with 1GB/s Bandwidth,” IEEE International Solid-State Circuits Conference, ISSCC96/Session 23/DRAM/Paper SP 23.6, pp. 378-379, Feb. 1996.
Nitta et al., “A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchial Square-Shaped Memory Block and Distributed Bank Architecture,” IEEE International Solid-State Circuits.
Conference, ISSCC96/Session 23/DRAM/Paper SP 23.5, pp. 376-377, Feb. 1996.
JEDEC Solid State Products Engineering Council, “Committee Letter Ballot,” JC-42.3-95-73, Item #633.13, Apr. 1995.
JEDEC Solid State Products Engineering Council, “Committee Letter Ballot,” JC-42.3-95-72, Item #633.12, Apr. 1995.
Kitsukawa et al., “256-Mb DRAM Circuit Technologies for File Applications,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, pp. 1105-1111, Nov. 1993.
Sugibayashi et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, pp. 1092-1098, Nov. 1993.
Taguchi et al., “A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture,” IEEE Journal of Solid-State Circuits, vol. 26, No. 11, pp. 1493-1497, Nov. 1993.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

256 Meg dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 256 Meg dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 256 Meg dynamic random access memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4117902

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.