Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
365208, 36523008, 365104, G11C 1140
The first input terminal of a differential amplification type sense amplifier is connected to a first memory cell array and the second input terminal thereof is connected to a second memory cell array. Each of the first and second memory cell arrays is formed of a plurality of memory cells arranged in a matrix form. Each of the memory cells in the first memory cell array and a corresponding one of the memory cells in the second memory cell array are provided in the form of pair for each bit. Complementary data is programmed into the paired memory cells according to programming data. In the data readout operation, the potential of data read out from the paired memory cells is amplified by means of the differential amplification type sense amplifier. First and second loads are connected to the first and second input terminals of the differential amplification type sense amplifier. The mutual conductances of the first and second loads are controlled so as to set the potential difference between the potentials of data read out from the paired memory cells selected in the first and second memory cell arrays smaller in the verify mode than in the normal readout mode.
patent: 4543500 (1985-09-01), McAlexander, III
patent: 4601017 (1986-07-01), Mochizuki et al.
"A 25ns 16K CMOS PROM Using a 4-Transistor Cell", Saroj Pathak, et al, 1985, IEEE Int'l Solid-State Circuits Conference, Digest of Technical Papers, pp. 162-163.
Kabushiki Kaisha Toshiba
Popek Joseph A.
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