AC Transient driver for memory cells

Details AC Transient driver for memory cells AC Transient driver for memory cells

1983-12-29

1986-02-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365242, 365155, G11C 700, G11C 800, G11C 1100

Patent

active

045702403

ABSTRACT:
A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.

REFERENCES:
patent: 4156941 (1979-05-01), Homma et al.
patent: 4168539 (1979-09-01), Anderson
patent: 4357687 (1982-11-01), Rufford
patent: 4369502 (1983-01-01), Isogai
patent: 4370736 (1983-01-01), Takahashi
patent: 4477885 (1984-10-01), Sharp
patent: 4488268 (1984-12-01), Toyoda
IBM Technical Disclosure Bulletin, "DI-Istor Speed-Up Word Drive With Resistor Word Bottom", by F. T. Blount et al., vol. 14, No. 6, Nov. 71, pp. 1734-1735.

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