Memory array architecture for flash memory
Memory array architecture utilizing global bit lines shared by m
Memory array architectures based on a triple-polysilicon...
Memory array cell reading circuit with extra current branch
Memory array having a reduced number of metal source lines
Memory array having a reduced number of metal source lines
Memory array having Frohmann-Bentchkowsky EPROM cells with a red
Memory array including multiple-gate charge trapping...
Memory array incorporating memory cells arranged in NAND...
Memory array of floating gate-based non-volatile memory cells
Memory array of pairs of nonvolatile memory cells using...
Memory array segmentation and methods
Memory array segmentation and methods
Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM
Memory array utilizing multi-state memory cells
Memory array with electrically programmable memory cells and ele
Memory array with field oxide islands eliminated and method
Memory array with field oxide islands eliminated and method
Memory array with inverted data-line pairs
Memory array with pseudo single bit memory cell and method