Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-04-17
1996-10-08
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518520, 36518525, G11C 1606, G11C 706
Patent
active
055638260
ABSTRACT:
A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
REFERENCES:
patent: 4884241 (1989-11-01), Tanaka
patent: 5138579 (1992-08-01), Tatsumi
patent: 5237534 (1993-08-01), Tanaka
patent: 5396467 (1995-03-01), Liu
IEE Proceedings G. Electronic Circuits & Systems, vol. 140, No. 2 Apr. 1993, Stevenage GB pp. 117-122, "Design and Analysis of a High Speed Sense Amplifier For Single-Transistor Nonvolatile Memory."
IEEE International Solid State Circuits Conference, vol. 31, Feb. 17, 1988, New York US pp. 120-121, "A 90ns 4Mb CMOS EEPROM."5
Driscoll; David M.
Morris; James H.
Golla Carla M.
Maccarrone Marco
Pascucci Luigi
Driscoll David M.
Mai Son
Morris James H.
Nelms David C.
SGS--Thomson Microelectronics S.r.l.
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