Memory array segmentation and methods

Details Memory array segmentation and methods Memory array segmentation and methods

2006-02-08

2009-11-10

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185010, C365S063000

Reexamination Certificate

active

07616489

ABSTRACT:
The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.

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patent: 2005/0110073 (2005-05-01), Spadea
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