Memory array with electrically programmable memory cells and ele

Details Memory array with electrically programmable memory cells and ele Memory array with electrically programmable memory cells and ele

1988-11-16

1992-03-24

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

365104, 365178, 357 235, G11C 1604, G11C 1712

Patent

active

050994514

ABSTRACT:
To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.

REFERENCES:
patent: 4618943 (1986-10-01), Aipperspach et al.
patent: 4758984 (1988-07-01), Yoshida
Terman, "Floating Avalanche-Injection Metal Oxide Semiconductor Device With Low-Write Voltage", IBM TDB, vol. 14, No. 12, May 1972, pp. 3721-3722.

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