Static information storage and retrieval – Floating gate – Particular biasing
Patent
1992-12-21
1994-06-07
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
365184, 36518901, G11C 1300
Patent
active
053195930
ABSTRACT:
An electrically programmable nonvolatile semiconductor memory which includes an array of programmable transistor cells, such as EPROM cells, which avoids the use of field oxide islands to provide electrical isolation. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supplying programming voltages to selected ones of the memory cells. Alternate ones of the select cells are initially programmed to a high threshold (inactive) state so as to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state.
REFERENCES:
patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5109361 (1992-04-01), Yim et al.
patent: 5204835 (1993-04-01), Eitan
Dinh Son
LaRoche Eugene R.
National Semiconductor Corp.
LandOfFree
Memory array with field oxide islands eliminated and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory array with field oxide islands eliminated and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array with field oxide islands eliminated and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-798699