Memory array with field oxide islands eliminated and method

Details Memory array with field oxide islands eliminated and method Memory array with field oxide islands eliminated and method

1993-09-24

1995-06-06

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365104, 365178, 257335, 257343, 257402, G11C 1140

Patent

active

054228441

ABSTRACT:
A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.

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patent: 4887238 (1989-12-01), Bergemont et al.
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5117389 (1992-05-01), Yiu

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