Memory array of pairs of nonvolatile memory cells using...

Details Memory array of pairs of nonvolatile memory cells using... Memory array of pairs of nonvolatile memory cells using...

2011-08-09

2011-08-09

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185050, C365S185280, C365S185290

Reexamination Certificate

active

07995385

ABSTRACT:
A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

REFERENCES:
patent: 5029131 (1991-07-01), Vancu
patent: 5111430 (1992-05-01), Morie
patent: 5999445 (1999-12-01), Rolandi et al.
patent: 6081449 (2000-06-01), Sekariapuram et al.
patent: 7567457 (2009-07-01), Nazarian et al.

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