Memory array of floating gate-based non-volatile memory cells

Details Memory array of floating gate-based non-volatile memory cells Memory array of floating gate-based non-volatile memory cells

2011-03-08

2011-03-08

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185050

Reexamination Certificate

active

07903465

ABSTRACT:
A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

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