Memory array segmentation and methods

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185180, C365S185030, C365S185280

Reexamination Certificate

active

07903464

ABSTRACT:
An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.

REFERENCES:
patent: 6771536 (2004-08-01), Li et al.
patent: 6847087 (2005-01-01), Yang et al.
patent: 7075140 (2006-07-01), Spadea
patent: 7184308 (2007-02-01), Kwon et al.
patent: 7212434 (2007-05-01), Umezawa
patent: 7245534 (2007-07-01), Goda et al.
patent: 2002/0158282 (2002-10-01), Li et al.
patent: 2005/0110073 (2005-05-01), Spadea
patent: 2005/0174852 (2005-08-01), Hemink

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