Memory array with inverted data-line pairs

Details Memory array with inverted data-line pairs Memory array with inverted data-line pairs

2011-07-19

2011-07-19

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185060, C365S185070, C365S185120

Reexamination Certificate

active

07983085

ABSTRACT:
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.

REFERENCES:
patent: 5734609 (1998-03-01), Choi et al.
patent: 5923587 (1999-07-01), Choi
patent: 6650567 (2003-11-01), Cho et al.
patent: 7710774 (2010-05-01), Chen et al.

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