Static information storage and retrieval – Floating gate – Particular connection
Patent
1999-08-09
2000-07-18
Tran, Andrew Q.
Static information storage and retrieval
Floating gate
Particular connection
3651852, 3651856, 36518512, 36518533, 365 63, 365 72, 365104, 257314, 257315, G11C 1604
Patent
active
060916338
ABSTRACT:
As a specific application of a new memory architecture, an array of non-volatile dual floating gate memory cells is arranged on a semiconductor substrate with global bit lines extending in a column direction that are either permanently connected, or connectable through transistor switches, to short source and drain diffusions that are oriented in the row direction between the global bit lines. Multiple columns of memory cells are positioned between the global bit lines. Bit selection lines oriented in the column direction are connected to the gates of select transistors within the memory cells. Word lines individually extend over one or two rows of floating gates. This arrangement provides a very small array that allows for future scaling. It also enables the use of metal lines strapped to the global bit line diffusions, and to polysilicon word lines to reduce their resistance, without imposing their larger pitch on other array elements.
REFERENCES:
patent: 4336603 (1982-06-01), Kotecha et al.
patent: 4380057 (1983-04-01), Kotecha et al.
patent: 4417264 (1983-11-01), Angle
patent: 4733394 (1988-03-01), Giebel
patent: 4855955 (1989-08-01), Cioaca
patent: 5003510 (1991-03-01), Kamisaki
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5159570 (1992-10-01), Mitchell et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5278439 (1994-01-01), Ma et al.
patent: 5297148 (1994-03-01), Harari et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5364806 (1994-11-01), Ma et al.
patent: 5411905 (1995-05-01), Acovic et al.
patent: 5412600 (1995-05-01), Nakajima
patent: 5414693 (1995-05-01), Ma et al.
patent: 5486714 (1996-01-01), Hong
patent: 5576567 (1996-11-01), Mori
patent: 5606521 (1997-02-01), Kuo et al.
patent: 5616510 (1997-04-01), Wong
patent: 5643814 (1997-07-01), Chung
patent: 5661053 (1997-08-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5714412 (1998-02-01), Liang et al.
patent: 5786612 (1998-07-01), Otani et al.
patent: 5812449 (1998-09-01), Song
patent: B15172338 (1992-12-01), Mehrotra et al.
Alberts et al., "Multi-Bit Storage FET EAROM Cell", IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, pp 3311-3314.
Kamiya et al., "EPROM Cell with High Gate Injection Efficiency", Int'l Electron Device Mtg., Technical Digest, Dec. 13, 1982, pp. 741-744.
Ma et al., "A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories", 1994 IEEE pp. 3.5.1 thru 3.5.4.
Pein et al, "Performance of the 3-D Sidewall Flash EPROM Cell", International Electron Devices Meeting Technical Digest, Washington DC, Dec. 5-8, 1993, pp. 2.1.1 thru 2.1.4.
Kuo et al., "TEFET--A High Density, Low Erase Voltage, Trench Flash EEPROM", 1994 Symposium on VLSI Technology, Honolulu, Jun. 7-9, 1994, pp. 51-52.
Cernea Raul-Adrian
Samachisa George
SanDisk Corporation
Tran Andrew Q.
LandOfFree
Memory array architecture utilizing global bit lines shared by m does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory array architecture utilizing global bit lines shared by m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array architecture utilizing global bit lines shared by m will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2043603