Dual-port random access memory having memory cell controlled by
Dual-port random access memory having reduced architecture
Dual-port semiconductor memory device
Dual-port SRAM in a programmable logic device
Dual-port SRAM in a programmable logic device
Dual-port static random access memory cell
Dual-port static random access memory having improved cell...
Dual-ported read SRAM cell with improved soft error immunity
Dual-voltage wordline drive circuit with two stage discharge
Dual-voltage wordline drive circuit with two stage discharge
Dynamic clock signal generating circuit for use in synchronous d
Dynamic logic memory addressing circuits, systems, and methods w
Dynamic logic memory addressing circuits, systems, and methods w
Dynamic logic memory addressing circuits, systems, and methods w
Dynamic memory
Dynamic memory circuit with improved sensing scheme
Dynamic memory having access transistor turn-off state
Dynamic memory with improved address counter for serial modes
Dynamic memory with increased access speed and reduced chip...
Dynamic memory with isolated digit lines