Dynamic memory circuit with improved sensing scheme

Details Dynamic memory circuit with improved sensing scheme Dynamic memory circuit with improved sensing scheme

1988-06-06

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Plural blocks or banks

365205, 365222, 36518901, 36523008, G11C 800, G11C 700

Patent

active

048796921

ABSTRACT:
A dynamic type memory circuit is provided with an improved write circuit which can write a desired data signal to a memory cell in a selected column in a first mode and to a plurality of memory cells in all the columns simultaneously in a second mode. The memory circuit includes a plurality of memory cell groups, a plurality of sense amplifier groups provided for the memory cell groups, a write circuit for operatively writing an input data signal to a plurality of memory cells simultaneously in at least one memory cell groups and a plurality of independent sense amplifier activation circuits provided for the sense amplifier groups.

REFERENCES:
patent: 4494222 (1985-01-01), White et al.
patent: 4680737 (1987-07-01), Oishi et al.
patent: 4758987 (1988-07-01), Sakui
patent: 4764901 (1988-08-01), Sakurai
patent: 4771406 (1988-09-01), Oishi et al.
patent: 4796234 (1989-01-01), Itoh et al.
patent: 4802134 (1989-01-01), Tsujimoto

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