Dynamic logic memory addressing circuits, systems, and methods w

Details Dynamic logic memory addressing circuits, systems, and methods w Dynamic logic memory addressing circuits, systems, and methods w

1998-09-24

1999-11-09

Mai, Son

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365233, 326 95, 326108, G11C 800

Patent

active

059827025

ABSTRACT:
A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12) aligned in an array. The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub. 0, TA6.sub. 0, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31). Each of the plurality of decoder conditional series discharge paths is connected to a corresponding one of the plurality of decoder precharge nodes and is operable in response to selected ones of the data signals from the plurality of predecoder inverters to discharge the precharge voltage at the corresponding decoder precharge node during a decoder evaluate phase. Each of the plurality of decoder inverters has an input coupled to a corresponding one of the plurality of decoder precharge nodes and an output for providing one of the plurality of wordline enable outputs. Lastly, one of the plurality of predecoders (PD2) further comprises a plurality of precharge output signal circuits (20), each coupled to a corresponding one of the plurality of predecoder precharge nodes and for providing a precharge output signal for commencing the decoder precharge phase of a group of the plurality of decoder precharge nodes.

REFERENCES:
patent: 4194130 (1980-03-01), Moench
patent: 5117133 (1992-05-01), Luebs
patent: 5258666 (1993-11-01), Furuki
patent: 5278802 (1994-01-01), Kersh, III et al.
patent: 5389835 (1995-02-01), Yetter
patent: 5412331 (1995-05-01), Jun et al.
patent: 5440243 (1995-08-01), Lyon
patent: 5459693 (1995-10-01), Komarek et al.
patent: 5483181 (1996-01-01), D'Souza
patent: 5530659 (1996-06-01), Anderson et al.
patent: 5541537 (1996-07-01), Kim et al.
patent: 5541885 (1996-07-01), Takashima
patent: 5572151 (1996-11-01), Hanawa et al.
patent: 5594371 (1997-01-01), Douseki
patent: 5602497 (1997-02-01), Thomas
patent: 5661675 (1997-08-01), Chin et al.
patent: 5703828 (1997-12-01), Park et al.
patent: 5821778 (1998-10-01), Bosshart
patent: 5831451 (1998-11-01), Bosshart

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