Static information storage and retrieval – Addressing – Multiple port access
Patent
1994-08-11
1996-02-20
Nelms, David C.
Static information storage and retrieval
Addressing
Multiple port access
36518904, 365154, 365203, 36518908, 365190, G11C 800
Patent
active
054935369
ABSTRACT:
A semiconductor memory circuit contains an array of memory cells, each of which contains a data latch formed of cross-coupled two inverters. First and second gate elements connected in series are placed between an output end of the latch and a reference point. Third and fourth gate elements connected in series are placed between the other output end and the reference point. Fifth, sixth and seventh gate elements connected in series are placed between the reference point and a read data line. During a write operation, while keeping the first and fourth gate elements and one of the second and third gate elements closed, a data to be stored is written in the latch through one of the pair of write data lines. During a read operation, while keeping the sixth and seventh gate elements closed, a stored data in the latch is read out through the read data line. Read and write operations can be performed without affecting the unselected memory cells, which reduces power dissipation during write and read operations.
REFERENCES:
patent: 4933899 (1990-06-01), Gibbs
patent: 5216636 (1993-06-01), Runaldue
patent: 5307322 (1994-04-01), Usami et al.
NEC Corporation
Nelms David C.
Tran Andrew Q.
LandOfFree
Dual-port random access memory having memory cell controlled by does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual-port random access memory having memory cell controlled by , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-port random access memory having memory cell controlled by will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1361518