Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1998-09-24
1999-12-28
Nelms, David
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
365203, G11C 800
Patent
active
060090375
ABSTRACT:
A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an N wordline array of memory cells (12). The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8) having wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub.0, TA6.sub.01, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31). Each of the predecoder inverters has an inverter input and an inverter output, and comprises a p-channel transistor and an n-channel transistor. For one of the plurality of predecoders the output of each of its plurality of predecoder inverters is connected to provide a data signal to gates of an integer number D of n-channel transistors through a respective set of conductors each having a conductor capacitance C, wherein the integer number D of n-channel transistors are located in the plurality of decoder conditional series discharge paths and wherein each of the integer number D of n-channel transistors has a first load capacitance when the transistor is disabled and a second and greater load capacitance when the transistor is enabled. Lastly, the p-channel transistor in each of the predecoder inverters in each of the one of the plurality of predecoders is dimensioned to provide a drive capability of current to a load capacitance no greater than a value approximately equal to: ((1*the second load capacitance)+((D-1)*the first load capacitance)+(D*C)).
REFERENCES:
patent: 4788457 (1988-11-01), Mashiko et al.
patent: 5117133 (1992-05-01), Luebs
patent: 5258666 (1993-11-01), Furuki
patent: 5389835 (1995-02-01), Yetter
patent: 5440243 (1995-08-01), Lyon
patent: 5459693 (1995-10-01), Komarek et al.
patent: 5483181 (1996-01-01), D'Souza
patent: 5530659 (1996-06-01), Anderson et al.
patent: 5541537 (1996-07-01), Kim et al.
patent: 5541885 (1996-07-01), Takashima
patent: 5572151 (1996-11-01), Hanawa et al.
patent: 5594371 (1997-01-01), Douseki
patent: 5602497 (1997-02-01), Thomas
patent: 5661675 (1997-08-01), Chin et al.
patent: 5696721 (1997-12-01), McAdams et al.
patent: 5708623 (1998-01-01), Choi
patent: 5821778 (1998-10-01), Bosshart
patent: 5831451 (1998-11-01), Bosshart
patent: 5838629 (1998-11-01), Kohno
Donaldson Richard L.
Ho Hoai V.
Lake Rebecca Mapstone
Nelms David
Texas Instruments Incorporated
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