Dynamic logic memory addressing circuits, systems, and methods w

Details Dynamic logic memory addressing circuits, systems, and methods w Dynamic logic memory addressing circuits, systems, and methods w

1998-09-23

2000-02-01

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365203, G11C 800

Patent

active

060210877

ABSTRACT:
A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12). The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODEBR SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.225). Each of the plurality of wordline enable outputs corresponds to a respective one of the integer number N of wordlines and is operable to assert an enabling signal to the respective one of the integer number N of wordlines. Each of the plurality of predecoders includes a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3) a plurality of predecoder conditional series discharge paths (e.g., TA5.sub.0, TA6.sub.01, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets includes a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31). Each of the plurality of decoder conditional series discharge paths is connected to a corresponding one of the plurality of decoder precharge nodes and is operable in response to selected ones of the data signals from the plurality of predecoder inverters to discharge the precharge voltage at the corresponding decoder precharge node during a decoder evaluate phase. Moreover, each of the plurality of decoder conditional series discharge paths in each of the plurality of decoder sets forms a multi-level tree structure, and a fan out ratio of transistors between a first and second level of the multi-level tree structure is greater than 2:1.

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