Dynamic memory with isolated digit lines

Details Dynamic memory with isolated digit lines Dynamic memory with isolated digit lines

1994-05-20

1996-04-09

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365203, 365207, 365149, 365190, G11C 800

Patent

active

055068111

ABSTRACT:
A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.

REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 4748349 (1988-05-01), McAlexander, III et al.
patent: 4916667 (1990-04-01), Miyabayashi et al.
patent: 5014245 (1991-05-01), Muroka et al.
patent: 5029137 (1991-07-01), Hoshi
patent: 5053997 (1991-10-01), Miyamato et al.
patent: 5193075 (1993-03-01), Hatano et al.
patent: 5227697 (1993-07-01), Sakagami
patent: 5235547 (1993-08-01), Kobayashi
patent: 5291432 (1994-03-01), Furutani

Affiliated with

Also associated with

Rating

Dynamic memory with isolated digit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic memory with isolated digit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic memory with isolated digit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-143880