Dual-port SRAM in a programmable logic device

Details Dual-port SRAM in a programmable logic device Dual-port SRAM in a programmable logic device

2006-01-31

2006-01-31

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

06992947

ABSTRACT:
Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

REFERENCES:
patent: 5307322 (1994-04-01), Usami et al.
patent: 6044034 (2000-03-01), Katakura
patent: 6400635 (2002-06-01), Ngai et al.

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