Reduction of ONO fence during self-aligned etch to eliminate pol
Reduction of orientation dependent oxidation for vertical...
Reduction of pad erosion
Reduction of poly depletion in semiconductor integrated circuits
Reduction of the aspect ratio of deep contact holes for...
Reference layer structure in a magnetic storage cell
Regulating resistor network, semiconductor device including...
Relaxed silicon germanium platform for high speed CMOS...
Relaxed silicon germanium platform for high speed CMOS...
Relaxed-pitch method of aligning active area to digit line
Reliable and scalable virtual ground memory array formed...
Reliable high voltage gate dielectric layers using a dual...
Reliable low resistance strap for trench storage DRAM cell using
Reliable semiconductor device and method of manufacturing...
Removable spacer technique
Removable spacer technology using ion implantation for...
Removable spacer technology using ion implantation to...
Removal of charged defects from metal oxide-gate stacks
Removal of silicon oxynitride on a capacitor electrode for...
Replacement gate process for making a semiconductor device...