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Reduction of ONO fence during self-aligned etch to eliminate pol

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduction of orientation dependent oxidation for vertical...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduction of pad erosion

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduction of poly depletion in semiconductor integrated circuits

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduction of the aspect ratio of deep contact holes for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent

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Reference layer structure in a magnetic storage cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Regulating resistor network, semiconductor device including...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Relaxed silicon germanium platform for high speed CMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Relaxed silicon germanium platform for high speed CMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Relaxed-pitch method of aligning active area to digit line

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reliable and scalable virtual ground memory array formed...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reliable high voltage gate dielectric layers using a dual...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reliable low resistance strap for trench storage DRAM cell using

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reliable semiconductor device and method of manufacturing...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Removable spacer technique

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Removable spacer technology using ion implantation for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Removable spacer technology using ion implantation to...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Removal of charged defects from metal oxide-gate stacks

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Removal of silicon oxynitride on a capacitor electrode for...

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Replacement gate process for making a semiconductor device...

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