Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-09-25
2007-09-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C438S593000, C438S622000, C438S626000, C438S631000, C438S637000
Reexamination Certificate
active
11242773
ABSTRACT:
According to one exemplary embodiment, a method of fabricating a virtual ground memory array includes forming a number of polysilicon segments on a gate dielectric layer, where the gate dielectric layer is situated on a substrate. The method further includes forming a number of bitlines in the substrate, where each of the bitlines is situated adjacent to at least one of the polysilicon segments, and where the bitlines are formed after the polysilicon segments. The method further includes forming a gap-filling dielectric segment over each of the bitlines. The method can further include removing the masking layer and a portion of the gap-filling dielectric segment, depositing an interpoly dielectric layer on the polysilicon segments and on a remaining portion of the gap-filling dielectric segment, and forming a second polysilicon layer on the interpoly dielectric layer.
REFERENCES:
patent: 6187624 (2001-02-01), Huang
patent: 6365456 (2002-04-01), Cereda et al.
patent: 2001/0000242 (2001-04-01), Huang
patent: 2001/0003663 (2001-06-01), Huang
Farjami & Farjami LLP
Fourson George
Garcia Joannie Adelle
Spansion LLC
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