Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-14
2001-03-20
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000
Reexamination Certificate
active
06204117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly, to a method of forming a capacitor of a DRAM cell using a hemispherical grain structure after the removal of silicon oxynitride.
2. Description of the Prior Art
Since the creation of the first integrated circuit in 1960, the density that can be fabricated on semiconductor substrates has steadily increased. In the late 1970s the number of devices manufactured on a chip exceeded the generally accepted definition of “very large scale integration, or VLSI”, that is more than 100,000 devices per chip. By 1990 this number had grown to more than 32 million devices per chip (16 Mbit DRAM), and it is generally acknowledged that the era of “ultra-large-scale integration, or ULSI” has begun.
A typical memory cell for each bit in a DRAM is shown in
FIG. 1A
, which includes a semiconductor substrate
10
having a lower capacitor electrode
12
, a bit line
14
, a gate electrode
16
, a source region
20
, a drain region
22
, etc. formed thereon. In effect, a DRAM memory cell is formed by a combination of a transistor, a capacitor and contacts to peripheral circuitry.
The advent of ULSI technologies has significantly and continuously decreased in size of memory cells used to manufacture integrated circuits. The reduction in the space available to imprint integrated circuits has in turn caused a reduction in the capacitor area, which further in turn, affects the reduction in the cell capacitance. In addition, the size of a chargeable space capable of being stored by the capacitor also decreases. The consequence of the reduction in the dimension of a semiconductor die causes the fabrication of a capacitor susceptible to particle interference.
Several DRAM cells have been developed to overcome such problems. For example, a capacitor with a hemispherical grain (HSG) silicon storage node has been developed to increase the surface area of the capacitor electrode. The HSG-Si is deposited by a low-pressure chemical vapor deposition (LPCVD) method at a transition temperature from amorphous-Si to polycrystalline-Si. Nevertheless, before the deposition of HSG-Si, for giga bit DRAM using 0.18 um technology and below, a silicon oxynitride (SiON) layer
24
(shown in
FIG. 1A
) is preferred as photo bottom anti-reflection coating (BARC) and etching hard mask for high aspect ratio stack capacitor formation. However, the removal of the SiON layer by conventional dry etching methods would destroy the structure of and induce HSG-Si loss on an amorphous silicon surface. That is, a problem associated with HSG grain adhesion reliability has been introduced. For example, as illustrated in
FIG. 1B
, the phenomena of HSG-Si loss or an incomplete HSG-Si coverage
30
over the surface of the lower capacitor electrode
12
is shown.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a capacitor of a DRAM cell using a hemispherical grain structure after a removal of a silicon oxynitride (SiON) layer by phosphoric acid (H
3
PO
4
) that substantially enhances the adhesion ability of the SiON layer onto amorphous-silicon surface. This new method is capable in overcoming all the drawbacks of the conventional methods by preserving their advantages as well.
In achieving the above objective and in accordance with the purpose of the present invention, as embodied and broadly described herein. An embodiment of the present invention includes a method of forming a capacitor, which comprises the steps of: Providing a semiconductor substrate having a semiconductor body formed thereon; forming a first insulating layer over the semiconductor body; patterning the first insulating layer to define a contact hole for the capacitor; depositing a first conductive layer over the first insulating layer and filling up the contact hole; forming a SiON layer on the first conductive layer; patterning the SiON layer and the first conductive layer to form a lower capacitor electrode; removing the SiON layer to expose the entire upper surface of the lower capacitor electrode; forming a second conductive layer over the entire exposed surface of the lower capacitor electrode; forming a second insulating layer along a surface of the resulting structure; and finally forming a third conductive layer over the second insulating layer.
REFERENCES:
patent: 5766995 (1998-06-01), Wu
patent: 6037220 (2000-03-01), Chien et al.
Chiou Jung-Chao
Wang Chuan-Fu
Tsai Jey
United Microelectronics Corp.
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