Removable spacer technique

Details Removable spacer technique Removable spacer technique

2001-12-19

2003-01-14

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S305000, C438S592000, C438S286000

Reexamination Certificate

active

06506642

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices with independently optimized transistor performance. The present invention has particular applicability in fabricating high density integration semiconductor devices with MOS-type transistors having a design rule of about 0.12 &mgr;m and below.
BACKGROUND OF THE INVENTION
As feature sizes of metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) devices are reduced into the deep sub-micron range, so-called “short-channel” effects arise which tend to limit device performance. Deep junctions, as provided in PMOS devices, and high on-resistance, are problematic for voltages less than 2V.
For p-channel MOS transistors of short-channel type, the major limitation on performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain region to the source region, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of shallow source/drain extensions driven just under the gate electrode region, while the heavily-doped drain region is laterally displaced away from the gate by use of a sidewall spacer on side surfaces of the gate electrode. Such structures are particularly advantageous in avoiding large lateral diffusion, and the channel length can be set precisely.
In order to reduce contact resistance and increase control speed, metal silicide layers are conventionally formed on source/drain regions. As device geometries continue to plunge into deep sub-micron range, the need to accurately control the thickness of sidewall spacers formed on side surfaces of gate electrodes becomes increasingly significant. For example, adverting to
FIG. 1
, a gate electrode
11
is formed over semiconductor substrate
10
with a gate dielectric layer
12
therebetween and the sidewall spacers
13
on sides surfaces thereof. Sidewall spacers
13
can comprise polycrystalline silicon, silicon oxide, a silicon nitride or a silicon oxynitride. Shallow source/drain extensions
14
are typically formed using the gate electrode as a mask before forming sidewall spacers
13
.
Subsequently, as shown in
FIG. 2
, ion implantation is typically conducted using the gate electrode
11
and sidewall spacers
13
as a mask to form moderately- or heavily-doped and deeper source/drain regions
21
. The thickness W of sidewall spacer
13
is significant in at least two respects. Initially, as shown in
FIG. 2
, the thickness W of sidewall spacer
13
controls the length of the shallow source/drain extension
14
. In addition, as shown in
FIG. 3
, the width W of sidewall spacer
13
controls the distance between metal silicide layer
30
and side surfaces of gate electrode
11
.
A semiconductor chip contains numerous transistors designed for different functionality. It is therefore, highly desirable to decouple the optimum characteristics of an n-channel transistor from a p-channel transistor, as well as decoupling performance of similarly doped n-type transistors or p-type transistors depending upon their function, such as maximizing drive current or optimizing short channel effects. In order to achieve optimum performance for individual transistors, whether or not they have the same or different conductivity type, it is necessary to selectively tailor the width of the sidewall spacers on the side surfaces of the gate electrodes of particular transistors. As device geometries shrink further into the deep sub-micron regime, the ability to optimize the functionality of the individual transistors becomes increasingly significant. Conventional processing techniques employing disposable spacers made of various materials, such as polysilicon, silicon oxides, silicon nitrides, silicon oxynitrides, and combinations thereof, have been implemented with varying degrees of success and efficiency.
There exists a continuing need for methodology enabling the fabrication of semiconductor devices comprising transistors, both MOS and CMOS transistors, which are individually tailored for optimum functionality in an efficient, simplified, cost effective manner fully compatible with conventional process flow and increasing manufacturing throughput and product yield.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an efficient method for fabricating a semiconductor device which enables optimizing the functionality of individual transistors.
Another advantage of the present invention is a method of fabricating a semiconductor device by tailoring the thickness of the sidewall spacers for individual transistors.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming first and second gate electrodes, each gate electrode having side surfaces, over first and second gate dielectric layers, respectively, over a substrate; forming a first sidewall spacer, having a first thickness, on the side surfaces of the first and second gate electrodes; selectively removing the first sidewall spacer from the side surfaces of the first gate electrode while leaving the first sidewall spacer on the side surfaces of the second gate electrode; and depositing a second sidewall spacer, having a second thickness, on the side surfaces of the first gate electrode and on the first sidewall spacers on the side surfaces of the second gate electrode.
Embodiments of the present invention comprise forming the first and second sidewall spacers from a dielectric material, such as a silicon oxide, a silicon nitride or a silicon oxynitride. Advantageously, the first and second sidewall spacers can be formed of the same dielectric material. Embodiments of the present invention include forming the first sidewall spacer at a thickness of about 600 Å to about 1,200 Å and forming the second sidewall spacer at a thickness of about 300 Å to about 900 Å, such that the total thickness of the first and second sidewall spacers is about 900 Å to about 1,500 Å. Advantageously, the selective removal technique of the present invention can be applied to CMOS transistors having difference conductivity type transistors, or to two transistors having the same conductivity type, to optimize their respective functionalities.
Embodiments of the present invention include removing the first sidewall spacer by etching, as by adjusting the etching conditions to achieve an anisotropic etching component and an isotropic etching component thereby, effectively removing the first sidewall spacer in an efficient manner without jeopardizing the integrity of the substrate surface. Etching can be effected using conventional etch recipes, such as a basic SF
6
etchant recipe. Etching can also be implemented using hot phosphoric acid.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are capable of

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