Reduction of ONO fence during self-aligned etch to eliminate pol

Details Reduction of ONO fence during self-aligned etch to eliminate pol Reduction of ONO fence during self-aligned etch to eliminate pol

1997-12-08

1999-08-03

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 21336

Patent

active

059337290

ABSTRACT:
A method (200) of making a flash memory device without poly stringers includes forming a stacked gate region (202) on a substrate (102) and forming one or more word lines (122a, 122b, 204) in the stacked gate region. The method further includes performing a self-aligned etch (206) in regions adjacent to the one or more word lines (122a, 122b). The self-aligned etch (206) includes etching an insulating layer (110, 206a) with a relatively high insulating layer-to-polysilicon layer selectivity to thereby reduce the height of the resultant insulative fence (126). The self-aligned etch (206) then concludes with etching a polysilicon layer (106a, 106b); due to the reduced insulative fence (126), no poly stringers are formed during the etching of the polysilicon layer (106a, 106b).

REFERENCES:
patent: 5258095 (1993-11-01), Nagata et al.
patent: 5427967 (1995-06-01), Sadjadi et al.

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