Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-10-15
2001-01-02
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S253000, C438S255000
Utility Patent
active
06168984
ABSTRACT:
Related Patent Activity—“A METHOD TO REDUCE CONTACT HOLE ASPECT RATIO FOR EMBEDDED DRAM ARRAYS AND LOGIC DEVICES, VIA THE USE OF A TUNGSTEN BIT LINE STRUCTURE” C. J. Wang, W. C. Chiang, both of Taiwan Semiconductor Manufacturing Corp, invention disclosure TSMC97-436, assigned to a common assignee.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to methods used to fabricate semiconductor devices, and more specifically a process used to reduce the aspect ratio of contact holes for logic and memory devices, integrated on a single semiconductor chip.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
One difficulty encountered when attempting to integrate logic cells, with memory cells that are comprised of embedded dynamic random access memory, (DRAM), devices, is the ability to open contact holes, to regions of a semiconductor substrate, in thick insulator layers. The DRAM devices, comprised of bit line structures, as well as stacked capacitor structures, both located overlaying the semiconductor substrate, require thick insulator layers, to successfully isolate these components from adjacent conductive features. In addition with the use of sub—0.25 um groundrules, the contact holes in the thick insulator layers can be designed to dimensions as narrow as 0.3 um, in diameter, resulting in contact hole aspect ratios of about 7 to 1. This high contact hole aspect ratio is not only difficult to create, via anisotropic reactive ion etching procedures, but also difficult to fill, using conventional chemical vapor deposition, or plasma deposition procedures.
This invention will describe a process for integrating logic devices, and embedded DRAM devices, in which the aspect ratio of a contact hole, opened in about 20,000 Angstroms of insulator layer, and used to expose active logic and array device regions, is reduced. This is accomplished by initially forming tungsten plug structures, in self-aligned contact openings, located between gate structures, in the embedded DRAM region, while also forming tungsten structures, in a lower portion of contact holes, used to expose active device regions in the logic area. An upper portion of the contact hole is then formed, overlying and exposing the tungsten structure, residing in the lower portion of the contact hole. The aspect ratio of the upper portion of the contact hole is now reduced, when compared to contact holes formed without the tungsten structure, in the lower portion of the contact hole. In addition this invention includes the formation of tungsten structures, on N type, as well as P type, regions. If N type doped, polysilicon structures were used in place of tungsten, a diode affect would occur as a result of the N type, polysilicon structure contacting a P type source/drain regions, of a PFET device. Thus the creation of a two stage contact hole, used to reduce the aspect ration of sub-micron diameter, deep contact holes, can also be used for both P type, and N type contacts, in logic regions, due to the use of tungsten filling of the lower portion of the contact holes. In addition this invention will offer a second iteration in which a two stage contact hole opening procedure, again used to reduce the aspect ratio of the contact hole is described, however for this iteration the first portion of the two stage contact hole opening, is formed after formation of the capacitor structure. In the first iteration the first portion of the two stage contact hole opening, was formed prior to formation of the capacitor structure. Prior art, such as Liang et al, in U.S. Pat. No. 5,716,881, describe a process using tungsten plugs to connect overlying, and underlying metal structures, however that prior art does not show the two stage contact hole formation, used in the present invention, featuring tungsten structures, located in a lower portion of contact holes, located in both logic and memory regions, and with the tungsten structures, overlying and contacting, both N type, and P type regions, in a semiconductor substrate.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a process for fabricating logic devices, and DRAM memory devices, on the same silicon chip.
It is another object of this invention to reduce the aspect ratio of narrow diameter contact holes, for logic and DRAM memory devices, created in thick insulator layers, via use of a two stage, contact hole formation procedure, and a two stage metal fill procedure, with a first iteration featuring the formation of the lower portion of the two stage contact hole, created prior to the formation of a capacitor structure, while a second iteration describes a two stage contact hole opening, in which the lower portion of the two stage contact hole opening is formed after formation of a capacitor structure.
It is still another object of this invention to initially form the lower portion of the contact holes, in a first insulator layer, exposing P type, and N type source/drain regions, in the region of the semiconductor substrate used for logic devices, while forming the lower portion of the contact holes, in the first insulator layer, in a region of the semiconductor substrate to be used for DRAM memory devices, with the lower portions of the contact holes, in the DRAM region, providing a self-aligned contact opening, exposing source/drain regions, located between the gate structures.
It is yet another object to fill the lower portion of the contact holes, located in both the logic and DRAM regions, with tungsten.
It is still yet another object of this invention to form a storage node contact hole, and a bitline contact hole, in upper levels of insulator layers, exposing the top surface of tungsten structures, residing in the lower portion of the contact holes, located in the DRAM memory region.
It is still yet another object of this invention to form the upper portions of the contact holes, in the upper levels of insulator layers, exposing the top surface of the tungsten structures, located in the lower portion of contact holes, in the logic region, and exposing the top surface of bitline and capacitor structures, located in the DRAM memory region.
In accordance with the present invention a fabrication process is described for integrating DRAM and logic devices on the same semiconductor chip, featuring a two stage contact hole opening procedure, used to reduce the aspect ratio for narrow diameter contact holes, in thick insulator layers, and featuring the filling of the lower portion of the contact holes, in both logic and DRAM memory regions, with tungsten. A first region of a semiconductor substrate is used for the logic devices, while a second region of the semiconductor substrate is used for the DRAM memory devices. An N well region, used for subsequent P channel, (PFET) devices, and a P well region, used for subsequent N channel, (NFET) devices, are formed in the logic region of the semiconductor substrate. Insulator filled, shallow trenches are next formed in the logic, as well as the DRAM memory region, for purposes of isolation. Polysilicon gate structures are formed, on a first gate insulator layer, in t
Chiang Ming-Hsiung
Chiang Wen-Chuan
Wu Cheng-Ming
Ying Tse-Liang
Yoo Chue-San
Ackerman Stephen B.
Dang Trung
Saile George O.
Taiwan Semiconductor Manufacturing Company
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