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Process for making a semiconductor integrated circuit device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making a semiconductor MOS transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making an EEPROM active area castling

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making and programming and operating a dual-bit mult

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making and programming and operating a dual-bit...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making bit selectable devices having elements...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making crosspoint memory devices with cells having a

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making embedded DRAM circuits having capacitor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making high performance MOSFET with scaled gate elec

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making improved MOS structure with hot carrier reduc

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making mask ROM using a salicide process and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making merged integrated circuits having salicide FE

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making new and improved crown-shaped capacitors...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent

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Process for making semiconductor device having nitride at silico

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making semiconductor device with epitaxially...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for making six-transistor SRAM cell local interconnect s

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for manufacture of low voltage power MOSFET device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for manufacture of MOS gated device with self aligned ce

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for manufacturing a CMOS circuit with all-around dielect

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Process for manufacturing a crystal axis-aligned vertical...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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