Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-05-26
2001-01-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S634000
Utility Patent
active
06168989
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a method for fabricating a crown-shaped capacitor structure on dynamic random access memory (DRAM) cells with increased capacitance, and with increased process window when etching the openings in an insulator for these crown-shaped capacitors. This increase in process window avoids overetching of the IPO-2 insulator over the bit lines that would otherwise lead to bit-line-to-capacitor electrical shorts in the conventionally made crown-shaped capacitors.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1s and 0s) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or chips). Each DRAM circuit (chip) consists in part of an array of individual memory cells that store binary data (bits) as electrical charge on the storage capacitors. Further, the information is stored and retrieved from the storage capacitors by means of switching on or off a single access transistor (by way of word lines) in each memory cell using peripheral addressing circuits, while the charge stored on the capacitors is sensed by way of bit lines and by read/write circuits formed on the peripheral circuits of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is formed either in the semiconductor substrate as a trench capacitor, or is built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip, and to form the adjacent capacitors on memory cells closer together. Unfortunately, as the cell size decreases, it becomes increasingly more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit.
One preferred method for making these capacitors is to make crown-shaped stacked capacitors which are built over the FETs and bit lines. However, when stacked capacitors are made using this traditional crown capacitor process, it is necessary to overetch the openings in an insulating layer for the capacitors to the cap node contact plugs to ensure that all plugs are open across the wafer. This overetching can erode the underlying insulating layer over the bit lines causing shorts between the bit lines and the capacitors. This shorting problem is best understood by reviewing the conventional process steps in
FIGS. 1 through 4
below.
In the prior art, a substrate
8
having partially completed DRAM devices is insulated with a first insulating layer
10
(commonly referred to as interpolysilicon oxide-1 or IPO-1). Bit lines
12
are formed on layer
10
and a planar second insulating layer
14
(IPO-2) is formed over the bit lines, as shown in FIG.
1
. The capacitors are now formed by etching openings to the source/drain areas on the substrate
8
for capacitor node contact plugs. The openings are filled with a doped polysilicon to form the plugs
20
, as shown in FIG.
2
. Referring to
FIG. 3
, an etch-stop layer
22
is deposited, and a thick third insulating layer
24
is deposited in which the crown capacitors will be formed. As still shown in
FIG. 3
, a photoresist mask
26
and anisotropic etching are used to etch openings
4
for the capacitors. The openings
4
are then etched in the third insulating layer
24
to the etch-stop layer
22
, and the layer
22
is removed to expose the node contact plugs
20
, as shown in FIG.
4
.
Because of the non-uniformity in the thickness of the third insulating layer
24
and because of the etch-rate non-uniformity across the wafer, overetching is necessary to expose all of the node contact plugs
20
across the wafer. Unfortunately, this overetching can erode the underlying IPO-2 layer
14
over the bit lines
12
, as depicted by point A in FIG.
4
. When the bottom electrodes are formed by depositing a conducting layer
32
, a reliability problem occurs in which the capacitor bottom electrode
32
can short to the bit line
12
at the eroded point A in the IPO-2
14
, as shown in FIG.
4
.
Several methods have been reported that increase the capacitance of the individual capacitors on a DRAM device. For example, in U.S. Pat. No. 5,811,331 to Ying, a method is described that forms a node contact that is recessed under an etch-stop layer
20
. The polysilicon node contact
32
(see
FIG. 9
) prevents etching of the IPO-2 layer
14
when the capacitor opening is misaligned to the node contact. Ying in U.S. Pat. No. 5,753,547 provides a method for making cylindrical capacitors which have a smooth top cylindrical surface and a uniform cylindrical height. U.S. Pat. No. 5,663,093 to Tseng et al. uses a sidewall-spacer technology to make a cylindrical capacitor having a central pillar that increases cell capacitance. Tseng et al. in U.S. Pat. No. 5,728,618 teach a method for making a larger capacitor for greater capacitance per cell area. In U.S. Pat. No. 5,821,141 to Huang, a method for making a cylindrical capacitor on a DRAM having pin-plug-profile node contacts that increase the photoresist alignment tolerance for making the cylindrical crown capacitor over the plug. Wang et al. in U.S. Pat. No. 5,759,892 teach a method for making cylindrical capacitors in which the capacitor node contact plugs are recessed and polysilicon sidewall spacers are formed to prevent the IPO-2 from being overetched near the bit lines.
However, although there has been considerable work done to increase the capacitor area on these miniature stacked capacitors, there is still a need to fabricate crown capacitors without overetching the IPO-2 layer using a simple and manufacturable process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to fabricate improved crown-shaped capacitors over bit lines (COB) for DRAM cells.
Another object of this invention is to utilize a polysilicon node contact plugs that extends above a second interpolysilicon oxide (IPO-2) to improve the process window and to minimize unwanted overetching that would otherwise cause reliability problems (bit line to capacitor shorts).
A method is described for making an array of crown-shaped capacitors that are more reliable than the traditional crown-shaped capacitors. The capacitors are formed on partially completed DRAM devices on a semi-conductor substrate. Typically the substrate is a single-crystal silicon substrate doped with a P type conductive dopant, such as boron (B). A relatively thick Field OXide (FOX) is formed surrounding and electrically isolating an array of device areas for memory cells on the substrate. The field oxide can be formed by the LOCal Oxidation of Silicon (LOCOS) method, commonly practiced in the industry. Other field oxide isolations can also be used, such as shallow trench isolation (STI) and the like to further increase circuit density. These partially completed DRAMs also include field effect transistors (FETS) in the device areas, one FET in each DRAM cell area. Typically the FETs consist of a thin gate oxide on the device areas, and gate electrodes formed from a patterned polycide layer. The FETs also have source/drain areas, one on each side and adjacent to the FET gate electrodes.
Continuing, a first insulating layer, commonly referred to as an interpolysilicon oxide-1 (IPO-1), is deposited over the device areas and the FO
Chiang Ming-Hsiung
Chiang Wen-Chuan
Wu Cheng-Ming
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Taiwan Semiconductor Manufacturing Company
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