Process for making improved MOS structure with hot carrier reduc

Details Process for making improved MOS structure with hot carrier reduc Process for making improved MOS structure with hot carrier reduc

1996-08-12

1997-09-02

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438719, 438965, H01L 21265

Patent

active

056630832

ABSTRACT:
An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

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Sze, S.M., "Device Miniaturization", Semiconductor Devices: Physics and Technology, 1985, pp. 216-219 month unknown.
Chang, C.S., et al., "High-Voltage FET Integrated Circuit Process", IBM Technical Disclosure Bulletin, vol. 16, No. 5, Oct., 1973, pp. 1635-1636.

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