Process for making merged integrated circuits having salicide FE

Details Process for making merged integrated circuits having salicide FE Process for making merged integrated circuits having salicide FE

1999-05-26

2000-06-13

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438239, 438253, 438592, H01L 218242

Patent

active

060749083

ABSTRACT:
A method for fabricating merged logic and DRAM integrated circuits (ICs) is achieved. An undoped polysilicon layer is deposited and protected over the logic region while a first polycide layer is deposited and patterned to form DRAM gate electrodes in the memory region. DRAM gate electrodes are then protected with an insulating layer and the undoped polysilicon is exposed and patterned to form logic gate electrodes. The source/drain areas and undoped polysilicon are doped by implanting and a titanium metal is deposited and annealed to form salicide FETs for logic circuits. This allows the IC to be fabricated having different FET gate-oxide thicknesses for the logic and memory circuits, different sidewall-spacer widths, self-aligned contacts, separate liner layers to optimize the formation of borderless metal contacts with reduced contact resistance, and different lightly doped drains in the logic and memory circuits to maximize the overall circuit performance. The merged integrated circuit is now completed to the first level of metal interconnections by forming bit lines and capacitors which are insulated, by forming metal contacts through the insulation, and by patterning a metal layer to form the first level of metal interconnections.

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patent: 5863820 (1999-01-01), Huang

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