Process for making embedded DRAM circuits having capacitor...

Details Process for making embedded DRAM circuits having capacitor... Process for making embedded DRAM circuits having capacitor...

2000-02-07

2002-08-20

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000

Reexamination Certificate

active

06436763

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for making capacitors under bit lines (CUBS) embedded dynamic random access memory (DRAM). The process is particularly useful for integrating (embedding) high-density memory with logic circuits on the same chip. Polysilicon landing plugs are used in the DRAM for the capacitor node contacts and for the bit line contacts to minimize the capacitor node leakage current. The capacitor-under-bit line (CUB) DRAM allows metal contacts with lower aspect ratio to be made to the logic circuits for lower resistance (R
C
) contacts and increased circuit performance.
(2) Description of the Prior Art
Capacitor-under-bit line (CUB) are more desirable than capacitor-over-bit line (COB) for embedding DRAM circuits with logic circuits because the contact to the logic circuits can be made with lower aspect ratios. However, one problem in making capacitor-under-bit line (CUB) DRAM is the need to pattern the top polysilicon electrode (plate) for the DRAM capacitor while providing reliable contact openings for bit line contacts between the closely spaced capacitors. This problem is best understood with reference to the schematic cross-sectional view a conventional CUB DRAM shown in
FIG. 13
making electrical contact to the N doped region
17
in the substrate
10
. Typically the DRAM cell areas are defined on the surface of a silicon substrate
10
by forming a field isolation
12
, such as shallow trench isolation (STI), that surrounds and electrically isolates the individual memory cell device areas. A gate oxide
14
is grown on the device areas and a first polysilicon layer
16
with an upper silicide layer
18
is deposited and patterned to form the FET polycide gate electrodes over the device areas and DRAM word lines over the STI
12
. A first etch-stop layer
22
(e.g., silicon nitride), a planar insulating layer
24
(comonly referred to as an interlevel dielectric or ILD layer), and a second etch-stop layer
26
are formed sequentially over the polycide gate electrodes. Contact openings
2
and
4
are etched in layers
26
,
24
and
22
for the capacitor node contacts and bit line contacts, respectively. A conductively doped second polysilicon layer is deposited and etched or polished back to form polysilicon plugs
30
in the contact apenings
2
and
4
. Next, a third polysilicon layer is used to form bottom electrodes
32
by various means, such as the crown shaped capacitors shown in
FIG. 13. A
thin interelectrode dielectric
34
(not explicitly shown in
FIG. 13
) is formed on the surface of electrode
32
, and a doped conformal fourth polysilicon layer
36
is deposited to form the capacitor top electrodes. The top electrodes
36
then patterned using a photoresist mask
38
. Unfortunately, as feature sizes are reduced for increased circuit density, it is also necessary to increase the capacitor height H (greater than 1.0 micrometers) to maintain a reasonable capacitance for storing charge. Therefore, the conventional photoresist mask
38
must be made sufficiently thick to protect the top portion of the capacitor electrodes when plasma etching is used to pattern the fourth polysilicon layer
36
. Because of the rough surface topography, the conventional photoresist layer is quite thick. This thick photoresist and the shallow depth of focus required for exposing high resolution images in the photoresist make it difficult to achieve the necessary resolution. This high resolution photoresist patterning and etching is a particular problem for the high aspect ratio openings
6
between the closely spaced capacitors in which polysilicon layer
36
must be etched over the bit line contact opening
4
for the common bit line contact between the adjacent memory cells. Also, the conventional method requires very accurate lithography alignment.
Several methods for making improved DRAM circuits have been reported in the literature. One method for making capacitor-under-bit line (CUB) DRAMs is described in U.S. Pat. No. 5,893,734 to Jeng et al. in which tungsten landing plugs are used to improve the electrical conductivity. In U.S. Pat. No. 5,897,350, Lee et al. teach a method for making a capacitor-over-bit line (COB) DRAM which circumvents the rough topography problem associated with making CUB DRAM structures. In U.S. Pat. No. 5,238,700 to Dennison et al. a method is described for making a CUB structure in which contact openings are etched through an insulating layer and through the capacitor polysilicon top electrode to the bit line landing plug. The polysilicon top electrode exposed in the bit line contact opening is then recessed and oxidized before the bit line contact is formed in the contact opening. Other methods for making DRAM capacitors are described in U.S. Pat. No. 5,902,126 to Hong et al. in which the capacitor is made over the bit line (COB), and in U.S. Pat. No. 5,888,863 to Tseng a method for fabricating capacitors in memory circuits in described, but do not address the bit line contacts. In U.S. Pat. No. 5,895,250 to Wu a method is described for making semicrown shaped capacitors, but the method for making bit line contacts is also not addressed.
However, there is still a need in the semiconductor industry to provide a very cost-effective process for making capacitor-under-bit lines embedded DRAM circuits that minimize the contact aspect ratio for logic circuits while increasing memory cell density and minimizing capacitance node leakage current.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to make capacitors under bit lines (CUB) embedded DRAM circuits with high performance logic circuits on the same chip that result in reduced aspect ratio contacts.
It is another object of the present invention to achieve the above objective using polysilicon plug contacts in the DRAM cells to minimize the capacitor node leakage currents while reducing the aspect ratio for the contacts to the logic circuits.
It is still another object of this invention, by a first embodiment, to use a bottom antireflecting coating (BARC) to fill the narrow spaces between adjacent stacked capacitors. This reduces the rough topography over the capacitors and allows an overlying photoresist layer to be exposed and developed with better definition (fidelity) for patterning the capacitor top electrodes. This provides more reliable contact openings to the bit line polysilicon land plug contacts.
Still another object of this invention, by a second embodiment, is to use a plasma enhanced chemical vapor deposition (PECVD) to deposit a non-conformal silicon oxide (SiO
X
) layer having a thicker portion on the top of the capacitors and a thinner portion at the base between the closely spaced capacitors. The PECVD oxide layer is anisotropically plasma etched back to form self-aligned openings between the capacitors. The PECVD oxide mask with these self-aligned openings is then used to etch open areas in the capacitor polysilicon top electrodes aligned over the polysilicon landing plugs for the bit line contacts.
Another object of the invention is to provide a process which is compatible with forming a hemispherical silicon grain (HSG) surface on the polysilicon bottom electrode of the capacitor to increase the capacitance.
The method for making these improved embedded DRAM logic circuits starts by providing a semiconductor substrate. Typically the substrate is a P
−
doped single-crystal silicon having a <100> crystallographic orientation. A field oxide is formed using shallow trench isolation (STI) to surround and electrically isolate device areas in logic regions and DRAM regions on the substrate. A thin gate oxide is formed on the device areas. A conductively doped first polysilicon layer is deposited on the substrate and a silicide layer is deposited and patterned to form field effect transistor (FET) polycide gate electrodes on the device areas, and word lines over the STI regions. Source/drain areas are formed b

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