Process for making bit selectable devices having elements...

Details Process for making bit selectable devices having elements... Process for making bit selectable devices having elements...

2006-05-16

2006-05-16

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S099000, C438S209000

Reexamination Certificate

active

07045421

ABSTRACT:
A method is used to make a bit selectable device having nanotube memory elements. A structure having at least two transistors is provided, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel. A trench is formed between one of the source and drain of a first transistor and one of the source and drain of a second transistor. An electrical communication path is formed in the trench between one of the source and drain of a first transistor and one of the source and drain of a second transistor. A defined pattern of nanotube fabric is provided over at least a horizontal portion of the structure and extending into the trench. An electrode is provided in the trench. A pattern of nanotube fabric is suspended so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a first transistor and one of the source and drain of a second transistor.

REFERENCES:
patent: 3448302 (1969-06-01), Shanefield
patent: 4845533 (1989-07-01), Pryor et al.
patent: 4853893 (1989-08-01), Eaton et al.
patent: 4876667 (1989-10-01), Ross et al.
patent: 4888630 (1989-12-01), Paterson
patent: 5198994 (1993-03-01), Natori
patent: 6044008 (2000-03-01), Choi
patent: 6048740 (2000-04-01), Hsu et al.
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6159620 (2000-12-01), Heath et al.
patent: 6183714 (2001-02-01), Smalley et al.
patent: 6198655 (2001-03-01), Heath et al.
patent: 6221330 (2001-04-01), Moy et al.
patent: 6232706 (2001-05-01), Dai et al.
patent: 6445006 (2002-09-01), Brandes et al.
patent: 6518156 (2003-02-01), Chen
patent: 6548841 (2003-04-01), Frazier et al.
patent: 6559468 (2003-05-01), Kuekes et al.
patent: 6574130 (2003-06-01), Segal et al.
patent: 6643165 (2003-11-01), Segal et al.
patent: 6645628 (2003-11-01), Shiffler et al.
patent: 6673424 (2004-01-01), Lindsay
patent: 6706402 (2004-03-01), Rueckes et al.
patent: 6750471 (2004-06-01), Bethune et al.
patent: 6759693 (2004-07-01), Vogeli et al.
patent: 6774052 (2004-08-01), Vogeli et al.
patent: 6781166 (2004-08-01), Lieber et al.
patent: 6784028 (2004-08-01), Rueckes et al.
patent: 6803840 (2004-10-01), Hunt et al.
patent: 6809465 (2004-10-01), Jin
patent: 6835591 (2004-12-01), Rueckes et al.
patent: 6836424 (2004-12-01), Segal et al.
patent: 6919592 (2005-07-01), Segal et al.
patent: 6942921 (2005-09-01), Rueckes et al.
patent: 2002/0130311 (2002-09-01), Lieber et al.
patent: 2002/0130353 (2002-09-01), Lieber et al.
patent: 2002/0172963 (2002-11-01), Kelley et al.
patent: 2002/0179434 (2002-12-01), Dai et al.
patent: 2003/0021141 (2003-01-01), Segal et al.
patent: 2003/0021966 (2003-01-01), Segal et al.
patent: 2003/0022428 (2003-01-01), Segal et al.
patent: 2003/0091825 (2003-05-01), Shiffler et al.
patent: 2003/0124325 (2003-07-01), Rueckes et al.
patent: 2003/0165074 (2003-09-01), Segal et al.
patent: 2003/0198812 (2003-10-01), Rueckes et al.
patent: 2003/0199172 (2003-10-01), Rueckes et al.
patent: 2003/0234407 (2003-12-01), Vogeli et al.
patent: 2003/0236000 (2003-12-01), Vogeli et al.
patent: 2004/0085805 (2004-05-01), Segal et al.
patent: 2004/0159833 (2004-08-01), Rueckes et al.
patent: 2004/0164289 (2004-08-01), Rueckes et al.
patent: 2004/0175856 (2004-09-01), Jaiprakash et al.
patent: 2004/0181630 (2004-09-01), Jaiprakash et al.
patent: 2004/0191978 (2004-09-01), Rueckes et al.
patent: 2004/0214366 (2004-10-01), Segal et al.
patent: 2004/0214367 (2004-10-01), Segal et al.
patent: 2005/0041465 (2005-02-01), Rueckes et al.
patent: 2005/0041566 (2005-02-01), Rueckes et al.
patent: 2005/0047244 (2005-03-01), Rueckes et al.
patent: 2005/0047277 (2005-03-01), Rueckes et al.
patent: 2005/0056825 (2005-03-01), Bertin et al.
patent: 2005/0056866 (2005-03-01), Bertin et al.
patent: 2005/0056877 (2005-03-01), Rueckes et al.
patent: 2005/0058834 (2005-03-01), Rueckes et al.
patent: 2005/0059176 (2005-03-01), Rueckes et al.
patent: 2005/0059210 (2005-03-01), Rueckes et al.
patent: 2005/0062035 (2005-03-01), Bertin et al.
patent: 2005/0062062 (2005-03-01), Bertin et al.
patent: 2005/0062070 (2005-03-01), Bertin et al.
patent: 2005/0063210 (2005-03-01), Segal et al.
patent: 2005/0063244 (2005-03-01), Bertin et al.
patent: 2005/0074926 (2005-04-01), Bertin et al.
patent: 2005/0095938 (2005-05-01), Rosenberger et al.
patent: 2005/0237781 (2005-10-01), Bertin et al.
patent: WO 01/03208 (2001-01-01), None
patent: WO 01/44796 (2001-06-01), None
patent: WO 2003/091486 (2003-11-01), None
patent: WO 2004/065655 (2004-08-01), None
patent: WO 2004/065657 (2004-08-01), None
patent: WO 2004/065671 (2004-08-01), None
Ajayan, P.M., et al., “Nanometre-size tubes of carbon,” Rep. Prog. Phys., 1997, vol. 60, pp. 1025-1062.
Ami, S. et al., “Logic gates and memory cells based on single C60electromechanical transistors,” Nanotechnology, 2001, vol. 12, pp. 44-52.
Avouris, Ph., “Carbon nanotube electronics,” Carbon, 2002, vol. 14, pp. 1891-1896.
Casavant, M.J. et al., “Neat macroscopic membranes of aligned carbon nanotubes,” Journal of Appl. Phys., 2003, vol. 93(4), pp. 2153-2156.
Choi, W.-B. et al., “Carbon-nanotube-based nonvolatile memory with oxide-nitride-film and nanoscale channel,” Appl. Phys. Lett., 2003, vol. 82(2), pp. 275-277.
Cui, J.B. et al., “Carbon Nanotube Memory Devices of High Charge Storage Stability,” Appl. Phys. Lett., 2002, vol. 81(17), pp. 3260-3262.
Dai, H. et al., “Controlled Chemical Routes to nanotube Architectures, Physics, and Devices,” J. Phys. Chem . B, 199, vol. 103, pp. 111246-11255.
Dehon, A., “Array-Based Architecture for FET-Based, Nanoscale Electronics,” IEEE Transactions on Nanotechnology, 2003, vol. 2(1), pp. 23-32.
Dequesnes, M. et al., “Calculation of pull-in voltages for carbon-nanotube-based nanoelectromechanical switches,” Nanotechnology, 2002, vol. 13, pp. 120-131.
Dequesnes, M. et al., “Simulation of carbon nanotube-based nanoelectromechanical switches,” Computational Nanoscience and Nanotechnology, 2002, pp. 383-386.
Fan, S. et al., “Carbon nanotube arrays on silicon substrates and their possible application,” Physica E, 2000, vol. 8, pp. 179-183.
Farajian, A. A. et al., “Electronic transport through bent carbon nanotubes: Nanoelectromechanical sensors and switches,” Phys. Rev. B, 2003, vol. 67, pp. 205423-1=205423-6.
Fischer, J.E. et al., “Magnetically aligned single wall carbon nanotube films: Preferred orientation and anisotropic transport properties,” Journal of Appl. Phys., 2003, vol. 93(4), pp. 2157-2163.
Franklin, N. R. et al., “Integration of suspended carbon nanotube arrays into electronic devices and electromechanical systems,” Appl. Phys. Lett., 2002, vol. 81 (5), pp. 913-915.
Fuhrer, M.S. et al., “High-Mobility Nanotube Transistor Memory,” Nano Letters, 2002, vol. 2(7), pp. 755-759.
Homma, Y. et al., “Growth of Suspended Carbon Nanotubes Networks on 100-nm-scale Silicon Pillars,” Appl. Phys. Lett., 2002, vol. 81(12), pp. 2261-2263.
Kinaret, J.M. et al., “A carbon-nanotube-based nanorelay,” Appl. Phys. Lett., 2003, vol. 82(8), pp. 1287-1289.
Lee, K.-H. et al., “Control of growth orientation for carbon nanotubes,” Appl, Phys. Lett., 2003, vol. 82(3), pp. 448-450.
Radosavlievic, M. et al., “Nonvolatile molecular memory elements based on ambipolar nanotube field effect transistors,” Nano Letters, 2002, vol. 2(7), pp. 761-764.
Robinson, L.A.W., “Self-Aligned Electrodes for Suspended Carbon Nanotube Structures,” Microelectronic Engineering, 2003, vol. 67-68, pp. 615-622.
Rueckes, T., et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing” Science, 2000, vol. 289, pp. 94-97.
Soh, H. T. et a

Affiliated with

Also associated with

Rating

Process for making bit selectable devices having elements... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for making bit selectable devices having elements..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for making bit selectable devices having elements... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3571952