Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-13
2002-07-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S306000, C257S295000, C438S197000
Reexamination Certificate
active
06426255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to a semiconductor integrated circuit device and a technique for manufacturing the same; and, more particularly, the invention relates to a technique which effective for use in a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Recently, with a view toward compensating for a decrease in the accumulative amount of charge in an information storing capacitor which occurs as a result of miniaturization of a memory cell, a so-called stacked capacitor structure, wherein an information storing capacitor-(capacitor) is disposed above a memory-cell selecting MISFET, has been adopted for the DRAM.
In the most up-to-date DRAM that has been miniaturized and integrated highly, however, it has come to be difficult to maintain a sufficient amount of accumulative charge simply by increasing the surface area of the information storing capacitor only by forming it in three dimensions. As a capacitative insulating film which constitutes a part of the information storing capacitor, the use of a high dielectric film or a ferroelectric film, such as PZT (PbZr
x
Ti
1-x
O
3
), PLT(PbLa
x
Ti
1-x
O
3
), PLZT, PbTiO
3
, SrTiO
3
, BaTiO
3
, BST(Ba
x
Sr
1-x
TiO
3
) or SBT(SrBi
2
Ta
2
O
9
) is therefore under investigation.
It is known, however, that since such a high dielectric film (ferroelectric film) contains a large amount of oxygen rich in reactivity, its properties tend to be deteriorated, for example, by the heat which occurs during processing, leading to a lowering of the production yield or deterioration of the retention properties (data retention properties).
When the above-described high dielectric film (or ferroelectric film) is employed for the capacitative insulating film of a capacitor, the conductive material used as an electrode material is composed mainly of a platinum metal, such as Pt (platinum), Ru (ruthenium) or Ir (iridium) or an oxide thereof.
It is the common practice to use anisotropic etching such as RIE (Reactive Ion Etching) for the patterning of a thin film made of the above-described platinum metal or oxide thereof to form an electrode. Upon anisotropic etching, a halogen gas, such as chlorine (Cl
2
) or a mixture thereof, with an inert gas, such as Ar (argon), is used as an etching gas.
However, the patterning of a thin film made of a platinum metal or an oxide thereof by dry etching is known to have an inherent problem in that it is difficult to obtain a desired pattern with good precision, because a large amount of reaction products having a low vapor pressure are deposited onto the side walls of a pattern. Various countermeasures to overcome this problem have been proposed.
For example, as a method to prevent deterioration of the pattern accuracy, which otherwise occurs in response to deposition of reaction products having a low vapor pressure onto side walls of the pattern upon dry etching of a Pt film and a PZT film by an Ar-added chlorine gas, a method has been proposed which comprises etching with a photoresist film, which has a round outer periphery at the top portion, as a mask, carrying out an appropriate amount of over-etching and then completely removing the side-wall deposited film which has remained on the side surfaces of the pattern. The above-described photoresist film having a round outer periphery at the top portion is formed by exposing a benzophenone novolac resist to light, developing it and then thermosetting while exposing it to ultraviolet rays as needed.
SUMMARY OF THE INVENTION
As described above, when a thin-film made of a platinum metal or oxide thereof which has a poor chemical reactivity is dry-etched with a photoresist film as a mask, a large amount of a reaction product is deposited on the side walls of the resist owing to a low vapor pressure of the reaction product. The reaction product deposited on the side walls of the resist during etching is not easily removed by ions, resulting in the problem that a pattern with a desired accuracy is not obtainable by etching with a resist mask and a wet rinsing is required subsequent to the etching in order to remove the reaction product.
An object of the present invention, therefore is to provide a technique for promoting miniaturization of a DRAM having a capacitor which uses, as an electrode material, a film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal.
The above-described object and the other objects, and novel features of the present invention will become apparent from the description in this specification and the drawings attached thereto.
Among the features disclosed in the present application, typical ones will be summarized as follows.
(1) The semiconductor integrated circuit device according to the present invention has a memory cell comprising a memory-cell selecting MISFET formed on the main surface of a semiconductor substrate, and a capacitor formed of a first electrode electrically connected to one of a source and a drain of the memory-cell selecting MISFET and a second electrode formed over the first electrode through a capacitative insulating film, wherein the first electrode of the capacitor is formed of a laminate film of a first conductive connector and a first conductor film formed thereover, each of the first conductive connector and the first conductor film is formed of a film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal and the first conductor film is thicker than the first conductive connector.
(2) In the semiconductor integrated circuit device of the present invention according to paragraph (1), a diameter of the lower end portion of the first conductive connector constituting a part of the first electrode is not less than that of its upper end portion and the diameter of the lower end portion of the first conductor film constituting another part of the first electrode is not greater than that of its upper end portion.
(3) In the semiconductor integrated circuit device of the present invention according to paragraph (1), the first conductive connector is formed of plural conductor films.
(4) In the semiconductor integrated circuit device of the present invention according to paragraphs (1) or (3), the first conductive connector constituting a part of the first electrode is formed of a conductive film formed by CVD or sputtering, while the first conductor film constituting another part of the first electrode is formed of a conductive film formed by plating.
(5) In the semiconductor integrated circuit device of the present invention according to paragraph (1), the capacitative insulating film of the capacitor is formed on the upper surface and side surfaces of the first electrode.
(6) In the semiconductor integrated circuit device of the present invention according to any one of paragraphs (1), (2), (3) and (5), the capacitative insulating film of the capacitor is composed mainly of a high dielectric film or ferroelectric fill having a perovskite or complex perovskite crystal structure.
(7) In the semiconductor integrated circuit device of the present invention according to paragraph (6), the second electrode of the capacitor is formed of a second conductor film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal.
(8) In the semiconductor integrated circuit device of the present invention according to paragraph (6), a silicon oxide insulating film and a metal interconnection are formed over the capacitor through a hydrogen-sparingly-permeable insulating film.
(9) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (f):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a dra
Asano Isamu
Nakamura Yoshitaka
Ohji Yuzuru
Saito Tatsuyuki
Yunogami Takashi
Hitachi , Ltd.
Le Thao P
Nelms David
LandOfFree
Process for making a semiconductor integrated circuit device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for making a semiconductor integrated circuit device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for making a semiconductor integrated circuit device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2914410