Process for making six-transistor SRAM cell local interconnect s

Details Process for making six-transistor SRAM cell local interconnect s Process for making six-transistor SRAM cell local interconnect s

1998-08-04

2000-08-08

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438618, H01L 218238

Patent

active

061001287

ABSTRACT:
A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.

REFERENCES:
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M. Helm et al., "A Low Cost, Microprocessor Compatible, 18.4 um.sup.2, 6-T Bulk Cell Technology for High Speed Srams", 1993 Symposium on VLSL Technology, pp. 65-66.

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