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Integrated circuit testing using a high speed data interface...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated circuit testing using segmented scan chains

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit using wireless communication to store...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Integrated circuit with a control input that can be disabled

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with a VLSI chip control and monitor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with alternately selectable state...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with blocking pin to coordinate entry...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with design for testability and method...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with embedded test functionality

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with emulation register in JTAG JAP

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with integrated debugging mechanism for...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Integrated circuit with integrated debugging mechanism for...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Integrated circuit with JTAG port, tap linking module, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with JTAG port, TAP linking module, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with on-chip data checking resources

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Integrated circuit with scan test structure

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with self-test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with self-testing circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with serial I/O controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with serial test interface and logic for load

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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