Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-10-31
2004-05-11
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06735730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a very large-scale integration circuit (referred to as “VLSIC” hereinafter) having a data path for executing a data operation and a controller for controlling the data path, and more particularly to a design for testability of an integrated circuit (IC) having a test plan generator unit for generating a test plan of a test control signal sequence for a data path.
2. Description of the Related Art
In recent years, it becomes harder to execute a test in function for checking faults in a VLSIC since scale and integration of VLSICs are increasing. Therefore, there has been a demand for reducing a cost of a test and enhancing a quality of the test. The functional test for checking the VLSIC includes a step of test generation and a step of test execution. The test generation is a step for producing a particular input sequence of an input vector series (i.e., test vector series) or an input vector set (i.e., test vector set) using a known test generation algorithm so as to be applied to a subject circuit of an IC under being tested. The input sequence used for testing the IC is also known as a test sequence or test pattern set.
By application of the particular input sequence, the faults in function of the examined circuit can be detected by detecting a change in the output sequence thereof. This is because, when there is a fault in the subject circuit, the output sequence will be different from that in the case where there is no fault in the circuit.
The test execution is a step for applying the test sequence obtained in the test generation step to the subject circuit to be checked, thereby examining the presence or absence of the faults. The cost of the test is evaluated depending on a time required for the test generation and test execution.
As an evaluation measure of the quality of the test, a fault detection efficiency (FDE) of the test sequence is available. The fault detection efficiency (FDE) indicates a rate of the number of the faults which can be detected by the test sequence generated using the test generation algorithm and the number of redundant (or undetectable) faults decided based on the test generation algorithm for the total number of all faults to be subjected to the test generation in the circuit, which is defined as:
FDE
=(
DF+RDF
)/
TF
wherein DF represents the number of detectable faults, RDF represents the number of faults decided to be redundant and TF represents the total number of the faults. In particular, a complete fault detection efficiency implies that the fault detection efficiency is a fault coverage rating of 100% (i.e., FDE=100%).
In recent years, a VLSIC is generally designed at a register transfer (RT) level, and a design-for-testability (i.e., test facilitating design) thereof is mainly carried out at the RT level. In general, the VLSIC designed at the RT level includes a data path
101
for carrying out a data process such as a data operation and a controller
102
for controlling the data path
101
as shown in FIG.
31
.
The data path
101
and the controller
102
are connected to each other through a status signal line
103
and a control signal line
104
. The status signal line
103
is provided for transmitting an operation state signal from the data path
101
to the controller
102
and the control signal line
104
is provided for transmitting a control signal from the controller
102
to the data path
101
for controlling a data flow. At the RT level, the data path
101
is described as circuit elements, for example, an arithmetic unit, a register and a multiplexer and a signal line connecting these circuit elements, and meanwhile the controller
102
is described as a state transition table.
The data path
101
has a data input portion directly connected to an external input DPI of the VLSIC and a control input portion directly connected to the control signal line
104
output from the controller
102
. On the assumption that an optional control signal can be supplied to the control input portion of the data path, when the test generation is carried out for testing the data path, a test sequence applied to the data input (DPI) and a test plan applied to the control input are generated for checking every circuit element. For this reason, when the test of the data path is carried out, it is necessary to supply the test plan to the control input portion which is connected to the internal control signal line
104
simultaneously with application of the test vector sequence to the data input portion of the data path.
It is noted here that the term “test plan” mentioned above implies a control vector sequence of a time series which serves to propagate (justify) the test vector from the external input (DPI) to the input port of a circuit element subject to a test and serves to propagate the output response of the circuit element to an external output DPO.
As an example of the method of supplying the test plan, there is a method of externally supplying the test plan from the outside of the VLSIC. Also, there is a method of internally supplying the test plan within the VLSIC. In the method of externally supplying the test plan from the outside of the VLSIC, an external input pin PI is added to the VLSIC and a switching circuit is provided on the control input portion of the data path to be directly connected to the added external input pin PI. Consequently, the test plan can be supplied from the outside of the VLSIC to the control input portion and the test can be carried out at an actual operation speed. In this method, however, there has been a problem that an external pin overhead becomes great.
On the other hand, in the method of internally supplying the test plan within the VLSIC, there is available a method of supplying the test plan fed from the original controller
102
. In this method, the test plan is supplied to the control input portion of the data path
101
using the control output signal in the same manner as a normal operation of the controller
102
in the VLSIC. In this case, the control output signal of the controller
102
to be supplied to the control input portion depends on the output function of the controller
102
. Therefore, it is not assured that all control signals for the test plan can be supplied to the control input portion of the data path. Moreover, there has been a problem that it takes considerable time to search the state transition series of the controller
102
for generating the control signal, resulting in that the test execution time is undesirably increased because of using the state transition series.
Furthermore, as another method of internally supplying the test plan in the VLSIC, there is available a method of supplying the test plan making use of a full scan controller (i.e., full-scan design-for-testability). In this method, a scan function is added to each of the flip-flops in the status register of the controller
102
so that all flip-flops in the state register are replaced by scannable flip-flops. Thus, the state register is replaced by a scannable register having scan-in and scan-out contacts so that the states of the flip-flops are externally controllable and observable through the scan-in and scan-out contacts of the scannable register. Thus, a control signal appearing for the test plan is generated from the control output of the controller
102
. However, the control signal generated from the control output of the controller
102
depends on the output function of the controller
102
. Therefore, it cannot be assured that all control signals of the test plan can be supplied to the control input portion of the data path. Furthermore, since the scan function is used, there has been a problem that the test cannot be carried out at an actual operation speed and the test execution time is increased, which results in a high cost of the test.
SUMMARY OF THE INVENTION
In order to solve the problems mentioned above, it is an essential object of the present invention to
Fujiwara Hideo
Masuzawa Toshimitsu
Ohtake Satoshi
Chung Phung M.
McDermott & Will & Emery
Semiconductor Technology Academic Research Center
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